1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device executing a self-refresh operation.
2. Related Art
A semiconductor memory device (DRAM) has recently been used for a portable data terminal. The portable data terminal is supplied with power from a battery, and thus it is required for reducing power consumption to attain a continuous long-term use.
A conventional DRAM, when in a self-refresh mode, forcibly executes the refresh operation for all row addresses including memory cells to which data has not been written, thereby bringing a flow of unnecessary self-refresh current (Icc6).
To solve this problem, in a DRAM having low power consumption and recently beginning to appear on the market, a memory space to which the self-refresh operation can be conducted can be designated by setting a mode register to thereby perform a partial self-refresh operation. Thus the unnecessary self-refresh current (Icc6) can be reduced.
Further, there has been proposed the one in which an internal register stores a start address and end address of a space to which the refresh operation is required to be executed, and then, the refresh operation is executed only to the stored addresses, and further, the cycle is made variable according to the size of the space to which the refresh operation is required to be executed, to thereby reduce the refresh current (Icc6) (for example, refer to Reference 1). Moreover, Reference 2 and Reference 3 disclose a technique concerning a control of the refresh operation in a semiconductor memory device.
However, in a DRAM with low power consumption, a mode register is required to be set externally or form outside in order to execute a partial self-refresh operation, resulting in a troublesome processing.
Further, Reference 1, information of the start address and end address is only stored in the internal register with respect to the space requiring no refresh operation. Accordingly, in case that the address of the space requiring no refresh operation is discontinuous, there arises a problem, for example, that the current reduction effect is small.
 less than References greater than 
Reference 1: Japanese Laid-Open Patent Publication No. 2001-338489.
Reference 2: Japanese Laid-Open Patent Publication No. 60-175294.
Reference 3: Japanese Laid-Open Patent Publication No. 3-66092.
The present invention is directed to solve the above-mentioned problem, and aims to provide a semiconductor memory device that automatically executes a partial refresh operation without requiring an external setting with a mode register or the like, thereby reducing self-refresh current.
A semiconductor memory device according to the invention includes a memory, a register, an address counter and a cycle generating circuit. The memory requires a refresh operation and has a predetermined number of divided memory spaces. The register stores information indicating whether the refresh operation is required or not with respect to each memory space. The address counter, with reference to the register, counts up an address while skipping an address for the memory space requiring no refresh operation to generate an address of the memory space to be refreshed. The cycle generating circuit, with reference to the register, generates a refresh cycle of which cycle varies according to the number of the memory spaces requiring the refresh.
The semiconductor memory device according to the present invention performs the self-refresh operation only to the memory space requiring the self-refresh operation, thereby being capable of reducing the self-refresh current (Icc6).